Napatech™, the leading provider of programmable Smart Network Interface Cards (SmartNICs) used for Data Processing Unit (DPU) and Infrastructure Processing Unit (IPU) services in telecom, cloud, enterprise, cybersecurity and financial applications worldwide, will showcase its SmartNIC-based offload solution for 5G User Plane Function (UPF) in collaboration with AMD and Advantech at MWC Americas in Las Vegas from September 28th through 30th, in AMD’s booth number W.1720.
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Unlike in most 4G networks based on purpose-built appliances, the 5G packet core is implemented as virtualized or cloud-native software running on servers located within edge and core data centers. As Communications Service Providers (CSPs) and enterprises scale up the deployments of their 5G networks, they face strong financial pressure to maximize the number of users that can be supported on each server, whether individual subscribers or IoT devices, thereby minimizing the net cost-per-user.
Within 5G packet core software, the subsystem that represents the highest compute workload is the User Plane Function (UPF), which performs critical packet inspection, routing and forwarding functions associated with connecting user and device traffic from the Radio Access Network (RAN) to the Data Network (DN). Since general-purpose server CPUs are not well suited to the performance and latency requirements of real-time packet processing, network operators and 5G core software vendors increasingly adopt solutions for offloading the UPF to accelerator cards which are optimized for executing such workloads.
Napatech addresses the key business challenges around packet core deployments through its new, integrated hardware/software solution that leverages an AMD Xilinx Virtex® field programmable gate array (FPGA) to deliver industry-leading UPF performance. The solution comprises a fully-offloaded UPF fast path implemented within Napatech’s Link-Inline™ software stack, running on an NT200 programmable PCI-Express (PCIe) SmartNIC based on an AMD Virtex® UltraScale+™ VU9P FPGA. The UPF data path is implemented as a port-to-port inline or “hairpinned” architecture, which ensures that following initial setup all flows are processed on the SmartNIC with no need to pass traffic to and from the server CPU, maximizing the overall performance of the system.
Using a single 200Gbps NT200 SmartNIC to sustain 100Gbps of full duplex traffic, the Napatech UPF Offload solution processes up to 140 million concurrent flows, with a flow learning rate greater than 1.5 million flows per second, achieving a total throughput of up to 85 million packets per second on stateful connections and ensuring full wire speed operation for typical packet sizes. In a representative use case analyzed by the company, the Napatech UPF offload solution enables network operators to support 75x more users per server than with a software-based UPF and 7x more users per server than with a competing ASIC-based SmartNIC.