Cadence Design Systems, Inc. announced its digital and custom/analog flows have achieved certification for TSMC’s latest N2 Design Rule Manual (DRM). Through this latest collaboration, the companies delivered new N2 process design kits (PDKs) to make it easy for customers to leverage the latest technologies from both companies, including Cadence AI technologies that improve designer productivity. Mutual customers are already designing innovative AI, hyperscale computing and mobile applications using the N2 PDKs, accomplishing design objectives, simplified analog process migration and faster time to market.
The complete, certified Cadence digital full flow includes the Innovus Implementation System, Quantus Extraction Solution and Quantus Field Solver, Tempus™ Timing Solution and ECO Option, Pegasus Verification System, Liberate Characterization Portfolio and Voltus IC Power Integrity Solution. For more information on the digital full flow,
The digital full flow supports all the latest TSMC N2 PDK requirements, offering customers several key new features. In addition, the Quantus Field Solver offers process modeling of comprehensive geometries and parasitic effects at N2, delivering highly accurate models for SRAM, memory, high-performance and sensitive designs. The Innovus Implementation System engines have been enhanced to achieve N2 design goals with optimal utilization, based on a predictable, convergent flow. The Pegasus Verification System for physical signoff delivers a productivity boost through a tight integration with Cadence’s Virtuoso Studio. Finally, the Voltus IC Power Integrity Solution provides IR analysis across the frontside layers, enabling customers to build a robust power network for IR drop closure.
The Cadence Cerebrus Intelligent Chip Explorer is also enabled on N2, which allows customers to spend less time on manual design processes, providing productivity improvements.
Cadence Custom/Analog Flow
The Cadence custom/analog flow, certified for TSMC’s N2 technology, is based on the Virtuoso Studio, which includes the Virtuoso Schematic Editor, Virtuoso ADE Suite and Virtuoso Layout Suite. Also included is the Spectre Simulation Platform, including the Spectre X Simulator and Spectre eXtensive Partitioning Simulator (XPS). This latest flow provides a complete suite of routing technology accurately covering all custom/analog topologies. For more information on the custom/analog flow.
The new Virtuoso ADE architecture has been augmented to let users manage up to tens of thousands of simulation tests in parallel on modern compute farms and public and private clouds, all while reducing the Virtuoso memory footprint. Enhanced verification methods have been added to ensure design robustness. Spectre FMC Analysis statistical technology quickly finds tail samples that can cause design failures. Additionally, new optimization algorithms are available to swiftly recenter migrated designs to new specification tolerances.
The Virtuoso Layout Suite has also been updated for efficient layout implementation on TSMC’s N2, providing performance enhancements like core editing commands, connectivity extraction, layout navigation and stream-out to abstract generation; enhanced abutment of analog cells with a track pattern assistant; a unique non-uniform grid-based, structured device placement methodology with interactive, assisted features for placement, routing, fill and insertion; device-level auto-routing to managed advanced-node complexities; automated DRM-compliant guard ring generation; integrated parasitic extraction and EM-IR checks; enhanced custom migration and reuse functionality; seamless place-and-route engine integration with Innovus Implementation System to improve quality of results (QoR).