IQM Quantum Computers, a global leader in superconducting quantum computers, announced a significant breakthrough in quantum error correction (QEC) with the introduction of “directional tile codes.” Developed in collaboration with researchers from Freie Universität Berlin, the University of Edinburgh, and Johannes Gutenberg-Universität Mainz, the framework achieves up to a 1,000-fold reduction in logical error rates compared to traditional surface codes without requiring modifications to standard hardware.
The announcement comes as IQM prepares for its planned Nasdaq listing via a merger with Real Asset Acquisition Corp. This milestone advances a foundational pillar of IQM’s technical roadmap, which targets large-scale, fault-tolerant quantum computing by 2030 and a path to scaling up to one million qubits.
Overcoming the Qubit Overhead Bottleneck on Flat Grid Layouts
Quantum systems are inherently sensitive to environmental noise and hardware imperfections. To achieve true quantum advantage, physical qubits must be bundled into “logical qubits” that repeatedly detect and correct errors throughout a computation. However, high-performance Quantum Low-Density Parity-Check (qLDPC) codes historically demanded complex, non-local check connectivity grids. These structures are impossible to permanently etch onto a flat, two-dimensional chip layout without overlapping routing lines, previously forcing manufacturers to look toward expensive 3D vertical wiring or long-range couplers.
Directional tile codes resolve this structural tension by compiling required stabilizer interactions into a dynamic, time-ordered sequence called a directional word. Rather than remaining stationary, check qubits utilize the intrinsic swap behavior of native iSWAP gates to travel dynamically across a uniform, square grid—moving North, East, South, and West to execute localized exchange sequences with data qubits. This native hardware orchestration allows the system to run highly efficient error-correcting codes while preserving a uniform, constant-depth syndrome extraction cycle regardless of the total code block scale.
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The technical findings published in detail on arXiv demonstrate that directional tile codes, such as the compact [[323, 14, 15]] code variant, yield massive architectural efficiencies:
1,000x Error Reduction: Drops the per-logical, per-round error rate by three orders of magnitude relative to standard rotated surface-code memories of equivalent block capacities.
Minimal Hardware Footprint: Achieves state-of-the-art error suppression at a footprint of roughly 30 total circuit qubits per logical qubit, evaluated under a realistic physical error rate of 0.001.
Automated Leakage Suppression: Naturally swaps the physical roles of data and check qubits at the end of each verification loop. This dynamic layout flushes out accumulated out-of-bounds energy states, preventing leakage noise from propagating across the processor.
Proactive Hardware Co-Design for Utility-Scale Deployments
“Quantum error-correction codes should not only be highly efficient; they should also be implementable on scalable and manufacturable hardware architectures. A close co-design of quantum error correction and hardware is a central element of IQM’s strategy,” said Dr. Inés de Vega, Chief Scientist of IQM Quantum Computers. “Directional tile codes represent a breakthrough in this direction, delivering up to a 1,000-fold reduction in logical error rates on near-term-sized IQM Crystal hardware while relying only on practical nearest-neighbour connectivity. This is a significant step toward scalable fault-tolerant quantum computing.”
We have been working on tile codes since 2025, as they are promising candidates due to their local checks, great parameters, and the many ways that exist to perform logical computation with them without adding connectivity requirements,” added Dr. Vincent Steffan, Senior Quantum Error-Correction Engineer at IQM Quantum Computers. “The key innovation of directional tile codes is that we are using dynamic syndrome extraction circuits to implement them on a square grid.”
The ability to implement these improvements on standard square qubit architectures makes directional tile codes directly relevant to IQM’s near-term hardware line, including the recently announced IQM Halocene product line engineered for QEC development. By establishing a commercial roadmap built for the practical realities of superconducting qubit manufacturing rather than ideal laboratory conditions, IQM continues to lead the industrial scaling of fault-tolerant quantum computing. Complete scientific data, hardware parameters, and corporate roadmap timelines can be reviewed through the official IQM Press Center.